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8. SPI Interface
8.1
Architecture
The SPI is a three-wire bi-directional asynchronous serial link. It works only in slave mode. The
protocol is the following:
Figure 8-1.
SPI Architecture
SPI_CSB
SPI_CLK
rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0
SPI_DIN
d7 d6 d5 d4 d3 d2 d1 d0
SPI_DOUT
8.2
SPI Protocol
On SPI_DIN, the first bit is a read/write bit. 0 indicates a write operation, while 1 is for a read
operation. The seven following bits are used for the register address and the eight last ones are
the write data. For both address and data, the most significant bit is the first one.
In case of a read operation, SPI_DOUT provides the contents of the read register, MSB first.
The transfer is enabled by the CSB signal active low. When no operation is being carried out,
SPI_DOUT is set high impedance to allow sharing of MCU serial interface with other devices.
The interface is reset at every rising edge of SPI_CSB in order to come back to an idle state,
even if the transfer does not succeed. The SPI is synchronized with the serial clock SPI_CLK.
Falling edge latches SPI_DIN input and rising edge shifts SPI_DOUT output bits.
Note that MCLK must run during any SPI write access from address 0x00 to 0x0D.
12
AT73C213
2744B–PMAAC–11-Apr-08
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